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High speed Flash memory The Flash program memory is organized in bit wide memory cells which can be used for storing both code and data constants.
Overview STR73xFxx Flexible clock control Two clock sources are used to drive the microcontroller, a main clock driven by an external crystal or ceramic resonator and an internal backup RC oscillator that operates at 2 MHz or 32 kHz. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. There are two internal Voltage Regulators for generating the 1.
Low voltage detectors The voltage regulator and Flash modules each have an embedded LVD that monitors the internal 1. Note: An external power-on reset must be provided ensure the microcontroller starts-up correctly. DMA 4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to peripheral, peripheral to memory and memory to peripheral transfers. Timebase timers TB The three bit timebase timers with 8-bit prescaler for general purpose time triggering operations.
Real-time clock RTC The RTC provides a set of continuously running counters driven by separate clock signal derived from the main oscillator.
I 2 C interfaces The two I 2 C Interfaces provide multi-master and slave functions, support normal and fast I 2 C mode kHz and 7 or bit addressing modes. Watchdog The bit watchdog timer protects the application against hardware or software failures and ensures recovery by generating a reset. External interrupts and wake-up lines 16 external interrupts lines are available for application use.
Block diagram STR73xFxx 3. STR73xFxx Block diagram 3. Table 4. Must be tied to ground Internal RC oscillator bias. You can only view or download manuals with. Sign Up and get 5 for free. Upload your files to the site. You get 1 for each file you add. Get 1 for every time someone downloads your manual.
Buy as many as you need. View and download manuals available only for. Register and get 5 for free. Upload manuals that we do not have and get 1 for each file. Get 1 for every download of your manual. Buy as much as you need. V DDA. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime.
The clock to each peripheral is gated with an individual control bit to optimize power usage by turning off peripherals any time they are not required. The STR71x requires an external 3. There are two internal Voltage Regulators for generating the 1. The main VR is switched off during low power operation.
Both the Main Voltage Regulator and the Low Power Voltage Regulator contain each a low voltage detection circuitry which keep the device under reset when the corresponding. This enhances the security of the system by preventing the MCU from going into an unpredictable state. This is because LVD operation is guaranteed only when V 33 is within the specification. The bit rate can be programmed up to 1 MBaud. It can be used by the application software for general timing functions.
The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. It includes Smartcard clock generation and provides support features for synchronous cards.
Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5. The two I 2 C Interfaces provide multi-master and slave functions, support normal and fast I 2 C mode kHz and 7 or bit addressing modes. It has an internal 8-bit baud rate generator. The Analog to Digital Converter, converts in single channel or up to 4 channels in singleshot or round robin mode.
Resolution is bit with a sampling frequency of up to 1 kHz. The input voltage range is The bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. Up to 14 external interrupts are available for application use or to wake up the application from STOP mode.
Caution: External pull-up to V 33 required to. See Figure 5. Reset state. Input level. Active inStdby. The pin will be tri-stated except when UART transmission is in progress. Refer to Table 8 on page They must be configured by software as Alternate Function see Table 8: Port bit configuration table on page 29 to be used by the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function see Table 8: Port bit configuration table on page During the reset phase, these pins are in input pull-up state.
When reset is released, they are configured as Output Push-Pull. When reset is released, they are configured as Hi-Z. During the reset phase, these pins are in input pull-down state.
During the reset phase, this pin is in input floating state. When reset is released, it is configured as Output Push-Pull. Welcome to ManualMachine.
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